요구사항이 negedge clk와 reset시에 0x34를 넣으라는 문제module top_module ( input clk, input reset, input [7:0] d, output [7:0] q); always @(negedge clk)begin if(reset) q

module top_module ( input clk, input reset, // Synchronous reset input [7:0] d, output [7:0] q); always @(posedge clk) begin if(reset) q RESET신호가 추가된 DFF (Synchronous)

module top_module ( input clk, input [7:0] d, output [7:0] q); always @(posedge clk) begin q 이전.. 코드랑 똑같은 8bit짜리 DFF

module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @(posedge clk) begin q 간단한 D Flip Flop