module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
이전.. 코드랑 똑같은 8bit짜리 DFF
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
이전.. 코드랑 똑같은 8bit짜리 DFF