Day 4 - 7-seg BCD Counter

// BCD Counter with modulo K

module alu_ex3 #(
    parameter N = 32,
    parameter K = 10,
    parameter M = 3
)(
    input   wire clk,
    input   wire rstn,
    output  wire [6:0]   bcd0,
    output  wire [6:0]   bcd1,
    output  wire [6:0]   bcd2
);

wire        roll0, roll1, roll2;
wire [ 3:0] led[0:2];

modulo_cnt #(.K(50000000))  u_cnt_base (.clk(clk), .rstn(rstn), .ena(1'b1 ), .led(      ), .roll(roll0));
modulo_cnt #(.K(10))        u_cnt_0    (.clk(clk), .rstn(rstn), .ena(roll0), .led(led[0]), .roll(roll1));
modulo_cnt #(.K(10))        u_cnt_1    (.clk(clk), .rstn(rstn), .ena(roll1), .led(led[1]), .roll(roll2));
modulo_cnt #(.K(10))        u_cnt_2    (.clk(clk), .rstn(rstn), .ena(roll2), .led(led[2]), .roll(     ));

SEG7_LUT u_seg7_0 (.iDIG(led[0]), .oSEG(bcd0));
SEG7_LUT u_seg7_1 (.iDIG(led[1]), .oSEG(bcd1));
SEG7_LUT u_seg7_2 (.iDIG(led[2]), .oSEG(bcd2));

endmodule

module modulo_cnt #(
    parameter K = 10,
    parameter N = 32
)(
    input wire clk,
    input wire rstn,
    input wire ena,
    output wire [4:0] led,
    output wire       roll
);

reg [N-1:0] cnt;

always @ (posedge clk or negedge rstn) begin
    if (~rstn)      cnt <= {N{1'b0}};
    else if (roll)  cnt <= {N{1'b0}};
    else if (ena)   cnt <= cnt + 1'b1;
end

assign roll = (cnt == K - 1) ? 1 : 0;

assign led = cnt[3:0];

endmodule

module SEG7_LUT (oSEG, iDIG);
input   [3:0]   iDIG;
output  [6:0]   oSEG;
reg     [6:0]   oSEG;

always @(iDIG)
begin
    case(iDIG)
        4'h1: oSEG = 7'b1111001;    // ---t---
        4'h2: oSEG = 7'b0100100;    // |     |
        4'h3: oSEG = 7'b0110000;    // lt   rt
        4'h4: oSEG = 7'b0011001;    // |     |
        4'h5: oSEG = 7'b0010010;    // ---m---
        4'h6: oSEG = 7'b0000010;    // |     |
        4'h7: oSEG = 7'b1111000;    // lb   rb
        4'h8: oSEG = 7'b0000000;    // |     |
        4'h9: oSEG = 7'b0011000;    // ---b---
        4'ha: oSEG = 7'b0001000;
        4'hb: oSEG = 7'b0000011;
        4'hc: oSEG = 7'b1000110;
        4'hd: oSEG = 7'b0100001;
        4'he: oSEG = 7'b0000110;
        4'hf: oSEG = 7'b0001110;
        4'h0: oSEG = 7'b1000000;
    endcase
end

endmodule

설명 적을 시간은 없었다